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ST75C520
HIGH SPEED FAX MODEM DATA PUMP
. . . . . . . .
PRELIMINARY DATA
ITU-T V.17, V.29, V.27ter, V.21 WITH FAX SUPPORT ITU-T V.23, V.21, BELL 103 V.17, V.29 (T104), V.27ter SHORT TRAINS V.33 HALF-DUPLEX 1800Hz OR 1700Hz CARRIER SINGLE CHIP COMPLETE DATA PUMP SINGLE 5V POWER SUPPLY : - TYPICAL ACTIVE POWER CONSUMPTION : 375mW - LOW POWER MODE (typ. 5mW) EXTENDED MODES OF OPERATIONS : - FULL IMPLEMENTATION OF THE V.17, V.33, V.29 AND V.27ter HANDSHAKES - AUTODIAL AND AUTOANSWER CAPABILITY - PROGRAMMABLE TONE DETECTION AND FSK V.21 FLAG PATTERN DETECTION DURING HIGH SPEED RECEPTION - PROGRAMMABLE CALL PROGRESS AND CALL WAITING TONE DETECTORS INCLUDING DTMF - PROGRAMMABLE CLASSTM DETECTION CAPABILITY - WIDE DYNAMIC RANGE (>48dB) - A-LAW VOICE PCM MODE VERSATILE INTERFACES : - PARALLEL 64 x 8-BIT DUAL PORT RAM - SYNCHRONOUS/HDLC PARALLEL DATA HANDLING - HDLC FRAMING SUPPORT - V.24 INTERFACE - FULL OPERATING STATUS REAL TIME MONITORING - FULL DIAGNOSTIC CAPABILITY - DUAL 8-BIT DAC FOR CONSTELLATION DISPLAY
DESCRIPTION The SGS-THOMSON Microelectronics ST75C520 chip is a highly integrated modem engine, which can operate with all currently used FAX group III standards up to 14400bps. Full V.21, V.23 and Bell 103 full duplex modem standards are implemented.
PQFP64 (Plastic Quad Flat Pack) ORDER CODE : ST75C520 PQFP
.
June 1995
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
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ST75C520 CONTENTS
I I.1 I.2 I.3 I.4 I.5 I.6 I.7 II III III.1 III.2 III.3 IV IV.1 IV.2 IV.3 V. V.1 V.2 V.3 V.4 V.5 VI VII VII.1 VII.2 VIII VIII.1 VIII.2 VIII.3 IX IX.1 IX.2 IX.3 IX.4 IX.5 IX.6 X XI XII XIII PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN CONNECTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HOST INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V.24 INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MISCELLANOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BOUNDARY SCAN INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USER INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DUAL PORT RAM DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND SET SHORT FORM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUS - REPORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DATA EXCHANGES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND SET DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STATUS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMAND ACKNOWLEDGE AND REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MODEM STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFFER OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE OPERATIONS OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRANSMIT OPERATIONS OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFFER STATUS AND FORMAT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . RECEIVE BUFFER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DATA BUFFER MANAGEMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEFAULT CALL PROGRESS TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . DEFAULT ANSWER TONE DETECTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELECTRICAL SCHEMATICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB DESIGN GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
3 3 3 4 4 4 4 5 5 6 6 6 8 10 10 10 11 11 11 14 16 17 17 18 27 27 28 34 34 34 38 38 38 39 39 40 40 40 42 42 42 43
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ST75C520
I - PIN DESCRIPTION I.1 - Pin Connections
EYEY TEST1 TEST2 EYEX TXA1 2 TXA2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 AGNDT VCM AVDD RXA2 RXA1 AGNDR VREFP VREFN EXTAL XTAL CLKOUT HALT RESET SCOUT BOS EOS MC0 RING GND RXD EBS 3 MC2 TXD CTS RTS V DD CLK CD
16 15 14 13 12 11 10 9 SA0 SA1 SA2 SA3 SA4 SA5 SA6 GND V DD SD0 SD1 SD2 SD3 SD4 SD5 SD6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
8
7
6
5
4
SR/W (SWR)
SDTACK
SCCLK
SDS (SRD)
INT/MOT
RDYS
SINTR
SCIN
GND
MC1
SD7
SCS
V DD
MCI
I.2 - Host Interface The exchanges with the control processor proceed through a 64 Bytes DUAL port RAM shared between the ST75C520 and the Host. The signals associated with this interface are :
Pin Name SD0..SD7 SA0..SA6 SDS (SRD) SR/W (SWR) SCS SDTACK SINTR RESET RING INT/MOT Type I/O I I I I OD OD I I I Description System Data Bus. 8-bit data bus used for asynchronous exchanges between the ST75C520 and the Host through the dual port RAM. High impedance when exchanges are not active. System Address Bus. 7-bit address bus for dual port RAM. System Data Strobe. Active low. Synchronizes all the exchanges. In Motorola mode initiates the exchange, active low. In Intel mode initiates a read exchange, active low. System Read/Write. In Motorola mode defines the type of exchange read/write. In Intel mode initiates a write exchange, active low. System Chip Select. Active low. System Bus Data Acknowledge. Active low. Open drain. System Interrupt Request. Active low. This signal is asserted by the ST75C520 and negated by the host. Open drain. Reset. Active low. Ring Detect Signal. Active low. Select Intel/Motorola Interface.
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ST75C520
I.3 - Analog Interface
Pin Name TXA1 TXA2 Type O O Description Transmit Analog Output 1 Transmit Analog Output 2. Outputs TXA1 and TXA2 provide analog signals with maximum peak to peak amplitude 2 x VREF, and must be followed by an external continous-time two pole smoothing filter (where VREF = VREFP - VREFN). Receive Analog Input 1 Receive Analog Input 2. The analog differential input peak to peak signal must be less than 2 x VREF. It must be preceded by an external continous-time single pole anti-aliasing filter. This filter must be as close as possible to the RXA1 and RXA2 Pins (where VREF = VREFP - VREFN). Analog Common Voltage (nominal +2.5V). This input must be decoupled with respect to AGND. Analog Negative Reference (nominal VCM - 1.25V). This input must be decoupled with respect to V CM. Analog Positive Reference (nominal V CM+1.25V). This input must be decoupled with respect to VCM.
RXA1 RXA2
I I
VCM VREFN VREFP
I/O I I
I.4 - V.24 Interface
Pin Name RTS CLK CTS RxD TxD CD Type I O O O I O Description Request to Send. Active low. Data Bit Clock. Falling edge coincides with DATA change. Clear to Send. Active low. Receive Data Transmit Data sampled with rising edge of CLK Carrier Detect. Active low.
I.5 - Miscellaneous
Pin Name XTAL EXTAL EYEX EYEY TEST1 TEST2 Type O I O O Description Internal Oscillator Output. Left open if not used. Internal Oscillator Input, or External Clock Constellation X analog coordinate Constellation Y analog coordinate To be left open To be left open
Note : The nominal external clock frequency of the ST75C520 is 29.4912MHz with a precision better than 5.10-5
I.6 - Boundary Scan Interface A set of 13 signals are dedicated for Testing the ST75C520 Component. These signals can be used in a development phase, associated with the SGS-THOMSON ST18932 Boundary Scan Development Tools, to Debug the application Hardware and Software. If not used all input signals must be grounded and all output signals left open.
Pin Name SCIN SCCLK SCOUT BOS EOS MC0..MC2 HALT MCI RDYS EBS CLKOUT Type I I O I I I I O O I O Description Scan Data Input Scan Clock Scan Data Output Begin of Scan Control End of Scan Mode Control Stop ST75C520 Execution Multicycle Instruction Ready to Scan Flag Enable Boundary Scan. Active low (must be set low in normal mode). Internal ST75C520 Clock (XTAL frequency divided by 2)
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ST75C520
I.7 - Power Supply
Symbol VDD GND AVDD AGNDT AGNDR Parameter Digital +5V (Pin 9, 25, 41). To be connected to AVDD (see below). Digital Ground (Pin 8, 24, 40). To be connected to AGNDT and AGNDR (see below). Analog +5V (Pin 62). To be connected to VDD (see below). Analog Transmit Ground (Pin 64). To be connected to GND (see below). Analog Receive Ground (Pin 59). To be connected to GND (see below).
AGNDT and AGNDR must be connected together as close as possible to the chip. GND and AGNDR board plans should be separated, then connected together as close as possible to the chip, at a single point. Similarly VDD and AVDD must ne connected as close as possible to the chip, at a single point. II - BLOCK DIAGRAMS II.1 - Functional Block Diagram
RXD TXD 16 CLK 14 1 2 TXA2 TXA1
V.17, V.29, V.27 FAX TRANSMITTER
15
ST75C520
HDLC TX
MUX
TX ANALOG
SD [0..7] (26 to 33)
DUAL RAM INTERFACE
DPLL
HDLC RX
V.17, V.29, V.27 FAX RECEIVER
RX ANALOG
60 RXA1 61 RXA2
SINTR 38
HANDSHAKE AND STATUS REPORT
TONE DETECTOR
V.24 INTERFACE
RING DETECTOR
V.21 FLAG DETECTOR
13 CD
12 CTS
11 RTS
10 RING
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75C52002.EPS
ST75C520
II.2 - Hardware Block Diagram
ST75C520
PROGRAM ROM 8K x 32
XTAL 55 EXTAL 56 BOUNDARY SCAN (42 to 51 - 53-54) EBS 3 12 ST18932 DSP CORE
RAM 2K x 16
FIFO 8 x 16
1 TXA2
IIR FIR
2 TXA1 58 V REFP
RESET 52 SA [0..6] (17 to 23) SD [0..7] (26 to 33) SDS (SDR) 34 SR/W (SWR) 35 SCS 36 SDTACK 37 SINTR 38 7 DPLL AND CONTROL
63 V CM 57 V REFN
8
DUAL PORT RAM 64 x 8
P A G E FIFO 8 x 16 FIR IIR FIR
60 RXA1 61 RXA2
S S S I O
CROM 8K x 16
E Y E
INT/MOT 39
V.24 INTERFACE 8-24 40 11
RTS
9-25 41 75C52003.EPS 59 62
AV
DD
12
CTS
13
CD
14
10
RING
16
15
7
6
5
4
64
AGNDR
CLK
TXD
DGND
RXD
III - ELECTRICAL SPECIFICATIONS Unless otherwise noted, electrical characteristics are specified over the operating range. Typical value are given for VDD = +5V and tamb = 25C. III.1 - Maximum Ratings (referenced to GND)
Symbol VDD VI, VIN II, IIN IO IOUT Toper Tstg Ptot Parameter DC Supply Voltage Digital or Analog Input Voltage Digital or Analog Input Current Digital Output Current Analog Output Current Operating Temperature Storage Temperature (plastic) Maximum Power Dissipation Value -0.3 to 7.0 -0.3 to (VDD + 0.3) 1 20 10 0, + 70 - 40, + 125 1000 Unit V V mA mA mA C C mW
Stresses above those hereby listed may cause damage to the device. The ratings are stress related only and functional operation of the device at conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Standard MOS circuits handling procedure should be used to avoid possible damage to the device.
III.2 - DC Characteristics VDD = 5.0V 5%, GND = 0V, Tamb = 0 to 70C (unless otherwise specified). III.2.1 - Power Supply and Common Mode Voltage
Symbol VDD IDD IDD-lp VCM Parameter Supply Voltage Supply Current (internal oscillator) Supply Current in Low Power Mode Common Mode Voltage Min. 4.75 Typ. 5 75 1 VDD/2 Max. 5.25 100 VDD/2 + 5% Unit V mA mA V
VDD/2 -5%
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AGNDT
TEST1
TEST2
EYEX
EYEY
DV
DD
ST75C520
III.2.2 - Digital Interface All digital pins except XTAL Pins.
Symbol VIL VIH II VOH VOL IOZ CIN Parameter Low Level Input Voltage High Level Input Voltage Input Current VI = VDD or VI = GND High Level Output Voltage (Iload = 2mA) Low Level Output Voltage (Iload = 2mA) Three State Input Leakage Current (GND < VO < VDD) Input Capacitance Min. -0.3 2.2 -10 2.4 -50 0 5 0.4 50 Typ. Max. 0.8 +10 Unit V V A V V A pF
0
Crystal oscillator interface (XTAL, EXTAL).
Symbol VIL VIH IL IH Parameter Low Level Input Voltage High Level Input Voltage Low Level Input Current GND < VI < VILmax High Level Input Current VIHmin < VI < VDD Min. 3.5 -15 15 Typ. Max. 1.5 Unit V V A A
III.2.3 - Analog Interface
Symbol VREF VCMOin VDIFin VCMOout VDIFout VOFFOut Rin Rout RL CL Parameter Differential Reference Voltage Input = VREFP - VREFN Input Common Mode Offset, v = (RXA1+RXA2)/2 - VCM Differential Input Voltage RXA1 - RXA2 Output Common Mode Voltage Offset = (TXA1+TXA2)/2 - VCM Differential Output Voltage TXA1 - TXA2 Differential Output DC Offset (TXA1 - TXA2) Input Resistance RXAx Output Resistance Load Resistance Load Capacitance TXAx TXAx TXAx 10 50 Min. 2.40 -300 -200 -100 100 Typ. 2.50 Max. 2.60 300 2 x VREF 200 2 x VREF 100 20 Unit V mV VPP mV VPP mV k k pF
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ST75C520
III.3 - AC Electrical Characteristics III.3.1 - Dual Port RAM Host Timing
WRITE-CYCLE TIMING NSCS READ-CYCLE TIMING
SA[0..6]
Valid Address
Valid Address
Motorola mode
SR/NW 1 7 4 1 9 4
NSDS
8 3 5 10 5 Valid Data OUT 2
12
SD[0..7]
Valid Data IN 2 6
6
NSDTACK 11 NSINTR
Intel mode
SR/NW (= NWRITE)
75C52004.EPS
NSDS (= NREAD)
Number 1 2 3 4 5 6 7 8 9 10 11 12 SDTACK Acknowledge Data Set-up Time
Description Address and Control Set-up Time
Min. 5
Typ.
Max. 20
Unit ns ns ns ns ns ns ns ns ns
10 0 5 0 45 70 45 35 50 15
Address and Control Hold Time Data Hold Time SDTACK Hold Time Write Enable Low State Access Inhibition High State (see Note) Read Enable Low State Read Data Access SINTR Clear Delay Data Valid to Tristate
ns ns ns
Note : A minimum delay of 70ns is required only from the rizing edge of NWRITE to the falling edge of the next selected NREAD or NWRITE.
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ST75C520
III.3.2 - Serial V.24 Interface Timing
CLK 1 TXD 3 Valid Data Out 4
Number 1 2 3 4 TXD to CLK Set-up Time TXD to CLK Hold Time RXD Valid to CLK Delay Time RXD Valid to CLK Hold Time 0 Description Min. 30 10 100 Typ. Max. Unit ns ns ns ns
2
Valid Data In
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RXD
ST75C520
IV - FUNCTIONAL DESCRIPTION IV.1 - System Architecture The chip allows the design of a complete FAX data-pump without any external component. Aversatile dual port RAM allows an easy interface with most micro-controllers. IV.2 - Operation IV.2.1 - Modes The modem implementation is fully compatible with FAX modulation recommendations. The modulation can be either Trellis Coded Modulation (TCM) as in V.17 14400, 12000, 9600, 7200bps rates, Quadrature Amplitude Modulation (QAM) as in V.29 9600, 7200, 4800 and V.27ter 4800 and 2400bps. Other modes of operation include tone and DTMF detection or generation, or speech mode. IV.2.2 - Transmitter Description The signal pulses are shaped in a dedicated filter further combined with a compromise transmit equalizer suited for transmission over strongly distorted lines. 3 different compromise equalizers are available and can be selected by software. IV.2.3 - Receiver Description The receiver section handles complex signals and uses a fractionally spaced complex equalizer. It is able to cope with distant modem timing drifts up to 10-4 as specified in the ITU-T recommendations. It also compensate for frequency drift up to 10Hz and for phase jitter at multiple and simultaneous frequencies. IV.2.4 - Tone Generator Description Four tones can be simultaneously generatedby the ST75C520. The tones are determined by their frequenciesand by the output amplitude level. A set of specific commands are also available for DTMF generation (using two of the four generators available). IV.2.5 - Tone Detector Description Sixteen tones can be simultaneously detected by the ST75C520. Each of the tones to be detected is defined by the coefficients of a 4th order programmable IIR. Detection thresholds are also programmable from -45dBm up to -10dBm. DTMF detection is also available and is performed by a specific filter section (that requires no programming). IV.2.6 - DTMF Detector Description A DTMF Detector is included in the ST75C520, it allows detectionof valid DTMF Digits. Avalid DTMF Digit is defined as a dual Tone with a total power higher than -35dBm, a duration higher than 40ms and a differential amplitude within 8dB (negative or positive). IV.2.7 - Voice Mode The ST75C520 voice mode allows the implementation of enhanced telephone functions like answering machines. The incoming samples (9600Hz), received from the line are PCM A-law coded and writen into the dual port RAM. The outpoing samples are decompressed using the same A-law and output to the telephone line. The voice mode is entered using a CONF command, it can be either transmit voice from the dual RAM Tx buffer to the telephone line, receive voice from the telephone line to the dual RAM buffer, or both of these functions simultaneously. The format of the signal is A-law coded without complementation of the even bits. The buffer mechanism, between the host micro-controler and the ST75C520, is identical to the mechanism used for parallel data exchanges except that it starts immediately after CONF command, the size of the transmit and received buffer, are and must be 8 bytes, there is no need for a XMIT command, and if an overrun or underrun condition occurs no error will be reported to the host processor. IV.2.8 - Analog Loop Back Test Mode In any transmission standard and serial data format, the ST75C520 can be configured for analog loop back test. IV.2.9 - Low Power Mode Sleep state can be attained by a SLEEP command. Activating the reset signal will wake up the datapump. When in sleep mode, the dual port RAM is unavailable and the clocks are disabled. When entering the low power mode, the ST75C520 stops its oscillator, all the peripherals of the DSP core are stopped in order to reduce the power consumption. The dual RAM is made inacessible. The ST75C520 can be awakened by a hardware reset. There is a maximum time of 20ms to restart the oscillator after waking up and an additional 5ms after the interrupt to be able to accept any command coming from the host.
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ST75C520
IV.2.10 - Reset After a hardware reset, or an INIT command, the ST75C520 clears all its internal memories, clears the whole dual RAM and starts to initialize the delta sigma analog converters. As soon as these initializations are completed, the ST75C520 clears the dual RAM address 0 (COMSYS), generates an interrupt IT6 (command acknoledge) and is programmed to send and receive tones, the bit clock and the sample clock are programmed to 9600Hz. The total duration of the reset sequence is about 5ms. After that time the ST75C520 is ready to execute commands sent by the host micro-controller. The durationof the reset signal shouldbe greater than 700ns. IV.3 - Modem Interface IV.3.1 - Analog Interface The modem designer must provide a proper hybrid interface to the ST75C520. An example of hybrid design is given in paragraphs XII and XIII. The inputs and outputs of the MAFE are differential, achieving thus a better noise immunity. The D/A converter output amplifier includes a single pole low-pass filter, its cut-off frequency is : Fc - 3dB # 19200Hz. Continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive components. IV.3.2 - Host Interface The host interface is seen by the micro as a 64x8 RAM, with additional registers accessible through an 8-bit address space. A selection Pin (INT/MOT) allows to configure the host bus for either INTEL or MOTOROLA type control signals. V - USER INTERFACE V.1 - Dual Port Ram Description The dual port RAM is the standard interface between the controller and the ST75C520, for either commands or data. This memory is addressedthrough a 7-bit address bus. The locations from $00 to $3F are RAM locations, while locations from $40 to $50 are control registers dedicated to the interrupt handling. Several functional areas are defined in the dual port RAM, namely : - the command area, - the report area, - the status area, - the data buffer area. V.1.1 - Mapping V.1.1.1 - Command Area The command area is located from $00 to $04. Address $00 holds the command byte COMSYS, and the next four locations hold the parameters COMPAR[0..3]. The command parameters must be entered before the command word is issued. Once the command has been entered, the command byte is reset and an acknowledge report is issued. A new command should not be issued before the acknowledgecounter COMACK isincremented. V.1.1.2 - Report Area The report area is located from address $05 to address $07. Location $05 holds the acknowledge counter COMACK. Each time a command is acknowledged, the report bytes COMREP[0..1] (if any) are written by the ST75C520 into locations $06 and $07, and the content of COMACK is incremented. This counter allows the ST75C520 to accurately monitor the command processing. V.1.1.3 - Status Area The statusarea is located from address $08 to $0A. The error status word SYSERR is located at address $08. This error status word is updated each time an error condition occurs. An optionalinterruption IT0 may additionally be triggered in the case of an error condition. Locations $09 and $0A hold the general status bytes STATUS[0..1]. The meaning of the bits depends on the mode of operation, and is described in Chapter VII. The third byte at address $0B holds the Quality Monitor byte STAQUA. V.1.1.4 - Optional Status Area The user can program (through the DOSR command) the three locations STAOPT[0..2] of the Optional Status Area ($0C to $0E) for the real time monitoring of three arbitrary memory locations. V.1.1.5 - Data Buffer Area The data area is made of four 8-byte buffers. Two are dedicated to transmission and the two others to reception. Each of the four buffers is attached to a status byte. the meaning of the status byte depends on the selected format of transmission. Within each buffer, D0 represents the first bit in time.
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V.1.2 - Interruptions The ST75C520 can generate 5 interrupts for the controller. The interrupt handling is made with a set of registers located from $40 to $50. The interruptions generated by the ST75C520 come from several different sources. Once the ST75C520 raises an interrupt, a signal is sent to the controller. The controller has then to process the interrupt and clear it. The interrupt source can be examined in the Interrupt Source Register ITSRCR located at $50. According to this status byte, the interrupt source can be determined.Then, writing a zero at one of the memory location $40 to $46 (Reset Interrupt Registers ITREST[0..6]) will reset the corresponding interrupt (and thus acknowledge it). These sources of interruptions can be masked globally or individually using the Interrupt Mask Register ITMASK located at $4F. The interrupt sources are : - IT0 : Error/Warning This signifies that an error has occurred and the error code is available in the error status byte SYSERR. This byte can be selectively cleared by the CSE command. - IT2 : Tx Buffer Each time the ST75C520 frees a buffer, this interrupt is generated. - IT3 : Rx Buffer Each time the ST75C520 has filled a buffer, this interrupt is generated. - IT4 : Status Byte This signifies that the status byte has changed and must be checked by the controller. - IT6 : Command Acknowledge This signifies that the ST75C520 has read the last command entered by the host, incremented the command counter COMACK, and is ready for a new command.
ITSRCR X D6 X D4 D3 D2 X D0
D0 = 1 D2 = 1 Dn = 1
ITMASK D7
IT0 Pending IT2 Pending ITn Pending
D6 X D4 D3 D2 X D0
D7 and D0 = 1 D7 and D2 = 1 ...................... D7 and D6 = 1
IT0 Enable D IT2 Enable D ..................... IT6 Enable D
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ST75C520
V.1.3 - Host Interface Summary
Address (hex) COMMAND AREA $00 $01-$04 REPORT AREA $05 $06-$07 STATUS AREA $08 $09-$0A $0B $0C-$0E DATA AREA $1C $1D-$24 $25 $26-$2D $2E $2F-$36 $37 $38-$3F INTERRUPT AREA $40-$46 $4F $50 Reset Interrupt Reg. Interrupt Mask Reg. Interrupt Source Reg. 7 1 1 ITREST[0..6] ITMASK ITSRCR Data Rx Buffer 0 Status Data Rx Buffer 0 Data Rx Buffer 1 Status Data Rx Buffer 1 Data Tx Buffer 0 Status Data Tx Buffer 0 Data Tx Buffer 1 Status Data Tx Buffer 1 1 8 1 8 1 8 1 8 DTRBS0 DTRBF0[0..7] DTRBS1 DTRBF1[0..7] DTTBS0 DTTBF0[0..7] DTTBS1 DTTBF1[0..7] Error Status General Status Quality Monitor Optional Report 1 2 1 3 SYSERR STATUS[0..1] STAQUA STAOPT[0..2] Acknowledge Counter Report 1 2 COMACK COMREP[0..1] Command Command Parameters 1 4 COMSYS COMPAR[0..3] Description Size (Byte) Mnemonic
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ST75C520
V.2 - Command Set The Command Set has the following attractive features : - user friendly with easy to remember mnemonics, - possibility of straightforward expansion with new commands to suit specific customer requirements, - easy upgrade of existing software using previous modem based SGS-THOMSON products. The command set has been designed to provide the necessary functional control on the ST75C520. Each command is classified according to its syntax and the presence/absence of parameters. In the case of a parametric command, parameters must first be written into the dual port RAM before the command is issued. Acknowledge and error report is issued for each command entered. V.2.1 - Command Set Summary V.2.1.1 - Operational Control Commands INIT Initialize. Initialize the modem engine. Set all parameters to their default values and wait for commands of the control processor. Non parametric command. IDT Identify. Return the product identification code. Non parametric command. SLEEP Turn to low power mode, the ST75C520 enters the low power mode and stops its crystal oscillator to reduce power consumption. In this mode all the clocks are stopped and the dual RAM is unreachable. HSHK Handshake. Begins the handshake se q u e nc e. Th e mo d em e n gine generates all the sequences defined in the ITU-T recommendations. A status report indicates to the control processor the state of the handsha ke. This command only applies to modes where a handshake sequence is defined. A CONF command must have been issued prior to the use of HSHK. Non parametric command. STOP FAX S to p. Stop FAX Half-dup le x transmitter. Non parametric command. SYNC FAX Synchronize. Start/Stop of FAX Half-du ple x rec eiver. P arame t ric command. CSE Clear Status Error. Selectively clears the Error status byte SYSERR. Parametric command. SETGN Set Gain. This command sets the global gain factor, which is used for the transmit samples. Parametric command.
V.2.1.2 - Data Communication Commands XMIT Tra n smit Da t a. S t art / st o p t he transmission of data in parallel mode. After a XMIT command, the ST75C520 sends the data contained in its dual port RAM. SERIAL Select Serial or Parallel Mode. This command selects the data source, i.e. either parallel or serial. The parallel mode uses a part of the dual port RAM as a double buffer. The serial mode uses the serial synchronous I/O. Parametric command. FORM Selects the Transmission Format (only in p a ra lle l mod e ). Th is c o mma nd configures the data interface for both receiver and transmitter according to the selected da ta fo rmat. Parametric command (HDLC or synchronous). In s er ia l mo d e , f o rmat is a lwa y s synchronous.
V.2.1.3 - Memory Handling Commands MW Memory Write. This command is used to write an arbitrary 16-bit value into the writable memory location currently specified by a parameter. Parametric command. Memory Read. This command allows the controller to read any of the ERAM or CROM (ST75C520 memory spaces) loc a tion wit ho ut in t erru pt in g t h e processor. Parametric command. Complex Read. This command allows the controller to read at the same time the real and imaginary part of a complex value stored in a double ERAM or CROM location. This feature is very interesting for eye pattern software control and for equalization monitoring. This command insures that the real and imaginary parts are sampled in the memory at the same time (integrity). Parametric command.
MR
CR
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V.2.1.4 - Configuration Control Commands CONF Configure. This command configuresthe modem enginefor data transmission and handshake procedures (if any) in any of the supported modes. The transmission parameters are set to their default values and can be modified with the MODC command. Parametric command. MODC Modify Configuration. This command allows modification of some of the parameters which have been set up by the CONF command. It can also be used to alter the mode of operations (short train). Parametric command. DOSR Define Optional Status Report. This command allows the modification of the optional status report located in the status area of the dual port RAM. One can thus select a particular parameter to be monit ored during all modes of operation. Parametric command. DSIT Define Status Interrupt. This command allows the programming of the status word bit that will generate an Interrupt to the controller. Parametric command. V.2.1.5 - Tone Generation Commands TONE Se le ct Ton e . P ro gra ms the ton e generator(s) for the desired default tone(s). Additional mnemonics provide quick programming of DTMF tones or other currently used tones. Parametric command. DEFT De fine Ton e . P ro g rams t h e t one generator(s) for arbitrary tone synthesis. Parametric command. Tone Generator Control. Enables or d isa b le s t h e t o n e ge n e rat o r(s ). Parametric command.
TGEN
IV.2.1.6 - Tone Detection Commands TDRC Read Tone Detector Coefficient. Read o n e To ne Det e c to r Co ef f icien t . Parametric command. Write Tone Detector Coefficient. Write o n e To ne Det e c to r Co ef f icien t . Parametric command. Read Tone Detector Wiring. Read one Tone Detector Wirin g co nnection. Parametric command. Write Tone Detector Wiring. Write one Tone Detector Wirin g co nnection. Parametric command. Clear Tone Detector Cell. Clear internal variables of a Tone Detector Cell. Parametric command.
TDWC
TDRW
TDWW
TDZ
V.2.1.7 - Miscellaneous Commands CALL JSR Call a Subroutine. Call a subroutine with one Parameter. Parametric command. Call a Low Level Subroutine. Call an internal subroutine with one parameter. Parametric command.
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V.3 - Command Set Short Form
CCI Command Mnemonic XMIT SETGN SLEEP HSHK INIT SERIAL CSE FORM DOSR TONE TGEN DEFT MR CR MW DSIT IDT JSR CALL TDRC TDRW TDWC TDWW TDZ CONF MODC STOP SYNC Value 0x01 0x02 0x03 0x04 0x06 0x07 0x08 0x09 0x0A 0x0C 0x0D 0x0E 0x10 0x11 0x12 0x13 0x14 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x20 0x21 0x25 0x26 Transmit Data Set Transmit Gain Power Down the ST75C520 Start Handshake Initialize (Software Master RESET) Enable/disable Data Serial Mode Clear Error Status Word Define Parallel Data Format Define Optional Status Report Generate Predefined Tones Enable Tone Generator Define Arbitrary Tone Memory Read Complex Read Memory Write Define Status Interrupt Return Product Identification Code Call a Low Level Subroutine Call a Subroutine Tone Detector Read Coefficient Tone Detector Read Wiring Tone Detector Write Coefficient Tone Detector Write Wiring Tone Detector Clear Cell Configure Modify Default Configuration FAX Stop Transmitter FAX Synchronize Receiver Description
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V.4 - Status - Reports V.4.1 - Status The ST75C520 has a dedicated status reporting area located in its dual port RAM. This allow a continuous monitoring of the status variables without interrupting the ST75C520. The first status byte gives the error status. Issuing of an error status can also be flagged by a maskable interrupt for the controller. The signification of the error codes are given in Chapter VII. The second and third status bytes give the general status of the modem. These status include for example the ITU-T circuit status and other items described in appendix. These two status can generate, when a change occurs, an interrupt to the controller ; each bit of the two byte word can be masked independently. The forth byte gives in real time a measure of the reception quality. This information may be used by the controller to monitor the quality of the received bits. Three other locations are dedicated for custom status reporting. The controller can program the ST75C520 for a real time monitoring of any of its internal RAM location. High byte or low byte of any word can thus be monitored. V.4.2 - Reports The ST75C520 features an acknowledge and report facility. The acknowledge of a command is monitored by a counter COMACK located in the dual port RAM. Each time a command is read from the command area, the ST75C520 will increment this counter. For instance, when a MR (Memory Read) command is issued, the data is first written in the report area, and the counter is incremented afterwards. This way of processing insures data integrity and gives additional synchronization between the controller and the data pump. V.5 - Data Exchanges The ST75C520 accepts many kinds of data exchange : the default mode uses the synchronous serial exchange. Other modes include HDLC framing support and synchronous parallel exchanges. Detailed description of the Data Buffer Exchanges modes is available in the paragraph IX. V.5.1 - Synchronous Parallel Mode The data exchanges are made through the dual port RAM and are byte synchronous oriented. The double buffer facilities of the ST75C520 allow an efficient buffering of the data. V.5.1.1 - Transmit Thecontrollermust firstfill at leastthe first bufferof data (Tx Buffer 0) with the bits to be transmitted. In order to perform this operation, the controller must first check the Tx Buffer 0 status word DTTBS0. If this buffer is empty, the controller fills the data buffer locations (up to 64 bits), and then writes in DTTBS0 the number of bytes contained in the buffer. The controller can then either proceed with the second buffer or initiate the transmission with a XMIT command. The ST75C520 copies the contents of the data buffer and then clears the buffer status word in order to make it again available, then generates an IT2 interrupt. The number of bytes specified by the status word is then queued for transmission. The process goes on with the two buffers until an XMIT command stops the transmission. After the finishing XMIT command has been issued, the last buffers are emptied by the ST75C520. Errors occur when both buffers are empty while the transmit bit queue is also empty. Error is signalled with an IT0 interruption to the controller. V.5.1.2 - Receive The controller should take care of releasing the Rx buffers before the Data Carrier Detect goes true. This is made by writing zero in the Rx Buffer Status 0 and 1. The ST75C520 then fills the first buffer, and oncefilled sets the status word with the number of bytes received and then generates an IT3 interrupt. It then takes control of the second buffer and operates the same way. The controller must check the status of the buffers and empty them. Once the data read, the controller must release the used buffer and wait for the next buffer to be filled. Error occurs when both buffers are declared full, and incoming bits continue to arrive from the line. Error is signaled by an IT0 interrupt. V.5.2 - HDLC Parallel Mode This mode implements part of the High Level Data Link Control formats and procedures. It is well suited for error correcting protocols like ECM or FAX T4/T30 recommendations.It supports the flagging generation,16-bit Frame Check Sequence,as well as the Zero insertion/deletion mechanism. V.5.3 - Serial Exchanges The other mode of operation for data exchanges is the Serial Synchronous Mode. In this mode, the data I/O is made through the V.24 interface (page 4). Even when using the parallel mode described above, the received bits are available on the ST75C520 RxD Pin. See paragraph VII.2.1 table for clock values.
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VI - COMMAND SET DESCRIPTION The appendixA containsthe description of the complete command set. Commands are presented according to the following form :
COMMAND
Opcode Hexadecimal digit
X X X
Command Name Meaning
COMMAND
X X
X
X
X
Synopsis Parameters
Short description of the functions performed by the command.
Field Name Byte X Pos. b..a xx * Value Definition Explanation of the parameter Default value
Field Byte Pos. Value
Name of the addressed bit field. Index (or address in the dual port RAM) of the parameter byte (from 1 to 4). Bit field position inside the parameter byte. Can either be a single position (from 0 to 7, 0 being LSB) or a range. Possible values for the bit (resp. bit field). Range means all values are allowed. A star means a default value. Values are expressed either under the form of a bit string, or under hexadecimal format. Call a Subroutine 19
0 0 0 1 1 0 0 1
CALL
Opcode:
CALL
Synopsis Parameters
CALL allows to execute a part of the ST75C520 firmware with a specific argument.
Field C_ADDR_L C_ADDR_H C_DATA_L C_DATA_H Byte 1 2 3 4 Pos. 7..0 7..0 7..0 7..0 Value Definition Low byte of the call address High byte of the call address Low byte of the argument High byte of the argument
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CONF
Opcode Synopsis 20
0 0 1
Configure for Operations
0 0 0 0 0
CONF
CONF allows the complete definition of the ST75C520 operation, including the mode of operation (tone, FAX transmit, FAX receive, voice transmit, voice receive, DTMF receive, ...) and the modem parameters (standard, speed, ...).
Field CONF_OPER CONF_ANAL CONF_PSTN CONF_AO CONF_V24 CONF_MODE Byte 1 1 1 1 1 2 Pos. 3..0 4 5 6 7 5..0 Value 0 1 0 1 0 1 0 1 1 3 4 7 8 9 C D Other 0 1 2 3 0 1 xx1 x1x 1xx xx1 x1x 1xx Definition Mode of operation, see below Normal mode Analog loop back (test mode only) PSTN (carrier detect set to -43/-48dBm) Leased line (carrier detect -33/-38dBm) Answer mode (FSK full duplex only) Originate mode (FSK full duplex only) Do not use RTS pin signal Use RTS pin signal Bell 103 (full duplex) V.21 (full duplex) V.23 (full duplex) V.27ter V.29 V.17 V.33 (half duplex) V.21 channel 2 Reserved No transmit equalizer Transmit equalizer #1 Transmit equalizer #2 Transmit equalizer #3 1800Hz carrier (V.17/V.33 only) 1700Hz carrier (V.17/V.33 only) 2400bps allowed (V.27) 4800bps allowed (V.27, V.29) 7200bps allowed (V.29, V.17) 9600bps allowed (V.29, V.17) 12000bps allowed (V.17, V.33) 14400bps allowed (V.17, V.33)
Parameters
CONF_TXEQ
2
7..6
CONF_CAR CONF_SP0
3 3
0 7..5
CONF_SP1
4
2..0
According with the 4 first bits of the CONF_OPER the ST75C520 is put into the following mode of operation.
CONF_OPER 0000* 0010 0100 0110 1000 1010 1111 Other Tones Voice Tone Voice Tones Voice Modem Not allowed Transmit Tones Tones DTMF DTMF Voice Voice Modem Not allowed Received
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CR
Opcode: 11
0 0 0
Complex Read
CR
0 1
1
0
0
Synopsis
CR allows the reading of a complex parameter. The parameter specifies the parameter address (for the real part : the imaginary part is next location). CR returns the high byte value of both real and imaginary part of the addressed complex parameter.
Field CR_ADDR_L CR_ADDR_H Byte 1 2 Pos. 7..0 7..0 Value Definition Low byte of the 16-bit address High byte of the 16-bit address
Parameters
CSE
Opcode: 08
0 0 0
Clear Error Status
CSE
0 0
0
1
0
Synopsis
CSE is used to clear the ST75C520 error status SYSERR byte. It is also used as an acknowledge to the error condition handler. For details, please refer to the corresponding appendix.
Field ERR_MASK Byte 1 Pos. 7..0 Value Definition Error mask See report appendix for detailed meaning
Parameters
DEFT
Opcode: 0E
0 0 0
Define Arbitrary Tone
DEFT
1 0
0
1
1
Synopsis Parameters
DEFT programs one of the four tone generator for arbitrary tone generation.The parameter is the frequency of the generated tone expressed in Hertz between 0 and 3600Hz.
Field TONE_GEN_SL TONE_FREQ_L TONE_FREQ_H TONE_SCALE Byte 1 2 3 4 Pos. 1..0 7..0 7..0 7..0 Value Definition Index of the tone generator (3..0) Low byte of the frequency High byte of the frequency (internally masked with 0F) Amplitude scaling factor (high byte) 3F gives the nominal amplitude
DOSR
Opcode: 0A
0 0
Define Optional Status Report
DOSR
0
0
0
1
0
1
Synopsis Parameters
DOSR specifies the address of the RAM variables to be monitored in the 3 locations STAOPT[0..2] of the dual port RAM. It also specifies the assignment within the 3 locations.
Field STA_OPT_ASS STA_OPT_ADL STA_OPT_ADH STA_OPT_HL Byte 1 2 3 3 Pos. 1..0 7..0 3..0 7 Value 0..2 Definition Index of the STAOPT destination Low byte of source address High byte of source address Select low byte of source Select high byte of source
0 1
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DSIT
Opcode: 13
0 0 0
Define Status Interrupt
DSIT
1 1
1
0
0
Synopsis
DSIT specifies the bit mask used with the STATUS[0] and STATUS[1] byte to generate an interrupt IT4 to controller. Each time a bit change happens in the status words, assuming the corresponding bit mask will be set, an interrupt will be generated.
Field STA_IT_MSK0 STA_IT_MSK1 Byte 1 2 Pos. 7..0 7..0 Value Definition Status[0] bit mask pattern Status[1] bit mask pattern
Parameters
Notes :
The default IT Status is 0x3F for STATUS[0] and 0xFF for STATUS[1].
FORM
Opcode: Synopsis Parameters 09
0 0 0
Select Transmission Format
FORM
0 1
0
1
0
FORM defines the type of transmission used. This format is valid only in the parallel data mode. The default format, unless specified, is synchronous.
Field X_SYNC Byte 1 Pos. 1..0 Value 00* 01 10 11 Definition Synchronous format (1) Transmit continous "1" HDLC framing Transmit continous "0" (1)
Notes :
1. This format is only valid for the transmiter.
HSHK
Opcode: 04
0 0 0 0
Handshake
HSHK
1 0 0
0
Synopsis Parameter
HSHK is used to command the ST75C520 to begin the transmit handshake sequence processing. The progress of the handshake is reported to the control processor. Non parametric command. Identify 14
0 0 0 1 0 1 0 0
IDT
Opcode: Synopsis Parameter
IDT
IDT Return the ST75C520 Hardware and Software release number. See paragraph VII.1.4. Non parametric command. Initialization 06
0 0 0 0 0 1 1 0
INIT
Opcode: Synopsis Parameter
Notes :
INIT
INIT forces the ST75C520 to reset all parameters to their default conditions and restart operations. Non parametric command.
This command makes a software reset of the ST75C520 and so cannot have the regular handshake protocol. It does not increment the COMACK, neither generate an Interrupt.
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JSR
Opcode: 18
0 0 0
Call a Low Level Subroutine
1 1 0 0 0
JSR
Synopsis Parameters
JSR allows to execute a part of the ST75C520 firmware with a specific argument.
Field C_ADDR_L C_ADDR_H C_DATA_L C_DATA_H Byte 1 2 3 4 Pos. 7..0 7..0 7..0 7..0 Value Definition Low byte of the call address High byte of the call address Low byte of the argument High byte of the argument
MODC
Opcode: 21
0 0 1
Modify Configuration
0 0 0 0 1
MODC
Synopsis
MODC allows modification of the configuration for special purpose. This command has no effect while in data mode, the parameters are just sampled when starting to transmit or receive. The value of these parameters are not affected when sending a CONF command.
Field MODC_SH MODC_FPT Byte 1 2 Pos. 6 3..2 Value 0* 1 00* 01 10 Definition Normal training sequence (1) Short training sequence No echo protection tone Long echo protection tone (180ms) Short echo protection tone (30ms)
Parameters
Notes :
1. Short train sequence must be preceded by at least one normal training sequence.
MR
Opcode: Synopsis Parameters 10
0 0 0 1
Memory Read
0 0 0 0
MR
MR allows the reading of a 16-bit parameter. The parameter specifies the parameter address.
Field MR_ADDR_L MR_ADDR_H Byte 1 2 Pos. 7..0 7..0 Value Definition Low byte of the 16-bit address High byte of the 16-bit address
MW
Opcode: 12
0 0 0
Memory Write
1 0 0 1 0
MW
Synopsis Parameters
MW allows the writing of a 16-bit parameter. The parameter specifies the address as well as the value to be transferred.
Field MW_ADDR_L MW_ADDR_H MW_VALUE_L MW_VALUE_H Byte 1 2 3 4 Pos. 7..0 7..0 7..0 7..0 Value Definition Low byte of the 16-bit address High byte of the 16-bit address Low byte of the 16-bit value High byte of the 16-bit value
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SERIAL
Opcode: Synopsis Parameters 07
0 0
Select Serial or Parallel Mode
0 0 0 1 1 1
SERIAL
SERIAL defines the data path, i.e. either serial or parallel.
Field TX_SDATA RX_SDATA Byte 1 1 Pos. 0 1 Value 0* 1 0* 1 Definition Use serial link for Tx Data Use parallel link for Tx Data Use only serial link for Rx Data Use also parallel link for Rx Data
Notes :
The received Bits always go to the output pin RXD, even when the RX_SDATA bit is set.
SETGN
Opcode: Synopsis 02
0 0 0
Set Output Gain
0 0 0 1 0
SETGN
SETGN is a command which sets the scaling factor of the transmit samples. It is used for setting the output level or for setting the level of the tone generators. The gain value is given in the form of a 2's complement 16-bit value.
Field GAIN_L GAIN_H Byte 1 2 Pos. 7..0 7..0 Value range FF* range 7F* Definition Low byte of the 16-bit gain value High byte of the 16-bit gain value
Parameters
Example
Gain (dB) 0 -1 -2 -3 -4 Gain (Hex) 7FFF 7214 65AC 5A9D 50C3 Gain (dB) -5 -6 -7 -8 -9 Gain (Hex) 47FA 4026 392C 32F5 2D6A Gain (dB) -10 -11 -12 -13 -14 Gain (Hex) 287A 2413 2026 1CA7 198A
SLEEP
Opcode: Synopsis Parameter
Notes :
Turn to Sleep Mode 03
0 0 0 0 0 0 1 1
SLEEP
SLEEP is used to force the ST75C520 to turn to low power mode. Non parametric command.
When receiving this command the ST75C520 will stop processing and so cannot have the regular handshake protocol. It does not increment the COMACK, neither generate an Interrupt.
STOP
Opcode: Synopsis Parameter
Notes :
FAX Stop Transmitter 25
0 0 1 0 0 1 0 1
STOP
STOP is used, in FAX Modes, to force the ST75C520 to turn off the transmitter in accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation. Non parametric command.
When receiving this command the ST75C520 will stop sending regular Data. In parallel mode this command must be preceded by a XMIT Stop command. In parallel mode the ST75C520 will wait until all the transmit buffers are sent before starting the Stop sequence.
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SYNC
Opcode: 26
0 0
FAX Synchronize the Receiver
SYNC
0
1
0
0
1
1
Synopsis
SYNC is used, in FAX Modes, to force the ST75C520 to Start/Stop the receiver in accordance with the corresponding ITU-T V.33/V.17/V.29/V.27recommendation.As soon as the ST75C520 receives the SYNC Start command it sets its receiver to detect the FAX synchronization signal.This command is the equivalent HSHK command for the receiver.
Field RX_SYNC Byte 1 Pos. 0 Value 0* 1 Definition Stop receiver Start receiver synchronization
Parameters
TDRC
Opcode: 1A
0 0
Tone Detector Read Coefficient
TDRC
0
0
1
1
0
1
Synopsis Parameters
TDRC Read one Coefficient of the selected Tone Detector Cell.
Field TD_CELL TD_C_ADDR Byte 1 2 Pos. 3..0 7..0 Value 0..F 0..B 10 20 Other Definition Tone detector cell number Biquad coefficient Energy coefficient Static level Reserved
The command answer is : Low Byte of Coefficient followed by High Byte of Coefficient.
TDRW
Opcode: 1B
0 0 0
Tone Detector Read Wiring
TDRW
1 1
1
1
0
Synopsis Parameters
TDRC Read Wiring of the selected Tone Detector Cell.
Field TD_CELL TD_W_ADDR Byte 1 2 Pos. 3..0 0 Value 0..F 0 1 Other Definition Tone detector cell number Biquad and energy input Comparator inputs Reserved
The command answer is: a) If TD_W_ADDR = 0 : - First Byte is the Node Number of the Signal connected to Biquadratic Filter input. - Second Byte is the Node Number of the Signal connected to the Energy estimator input. b) if TD_W_ADDR = 1 : - First Byte is the Node Number of the Signal connected to Comparator Negative input. - Second Byte is the Node Number of the Signal connectedto the Comparator Positive input.
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TDWC
Opcode: 1C
0 0
Tone Detector Write Coefficient
TDWC
0
0
1
1
1
0
Synopsis Parameters
TDWC Write one Coefficient of the selected Tone Detector Cell.
Field TD_CELL TD_C_ADDR Byte 1 2 Pos. 3..0 7..0 Value 0..F 0..B 10 20 Other Definition Tone detector cell number Biquad coefficient Energy coefficient Static level Reserved Low byte of coefficient High byte of coefficient
TD_COEFL TD_COEFH
3 4
7..0 7..0
TDWW
Opcode: 1D
0 0 0
Tone Detector Write Wiring
TDWW
0 1
1
1
1
Synopsis Parameters
TDRC Write Wiring of the selected Tone Detector Cell.
Field TD_CELL TD_W_ADDR Byte 1 2 Pos. 3..0 0 Value 0..F 0 1 Other Definition Tone detector cell number Biquad and energy input Comparator inputs Reserved
If TD_W_ADDR = 0 (Select Biquad and Energy Inputs) Parameters
Field TD_W_ERN TD_W_BIQ Byte 3 4 Pos. Value 0..3F 0..3F Definition Energy estimator signal input Biquad filter signal input
If TD_W_ADDR = 1 (Select Comparator Inputs) Parameters
Field TD_W_CN TD_W_CP Byte 3 4 Pos. Value 0..3F 0..3F Definition Negative comparator signal input Positive comparator signal input
TDZ
Opcode: 1E
0 0 0
Tone Detector Clear Cell
TDZ
1 0
1
1
1
Synopsis
TDZ Clears all internal variables of one Tone detector cell including Filter local variables and energy estimator. This command must be sent after changing coefficients of a cell to avoid instability.
Field TD_CELL Byte 1 Pos. 3..0 Value 0..F Definition Tone detector cell number
Parameters
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TGEN
Opcode: Synopsis Parameters 0D
0 0
Enable/disable Tone Generators
0 0 1 1 0 1
TGEN
TGEN causes the ST75C520 to enable or disable the four tone generators.
Field TONE_0_ENA TONE_1_ENA TONE_2_ENA TONE_3_ENA Byte 1 1 1 1 Pos. 0 1 2 3 Value 0* 1 0* 1 0* 1 0* 1 Definition Generator #0 disabled Generator #0 enabled Generator #1 disabled Generator #1 enabled Generator #2 disabled Generator #2 enabled Generator #3 disabled Generator #3 enabled
TONE
Opcode: Synopsis 0C
0 0 0
Predefined Tones
0 1 1 0 0
TONE
TONE programs the tone generators for the predefined tones. The tone generators #0 and eventually #1 are reprogrammed with this command. Eventually the tone generator #0 and #1 are enabled. Using a value not in the following table will disable tone generator #0 and #1.
Field TONE_SELECT Byte 1 Pos. 5..0 Value 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 Definition DTMF 0 (941 & 1336Hz) DTMF 1 (697 & 1209Hz) DTMF 2 (697 & 1336Hz) DTMF 3 (697 & 1477Hz) DTMF 4 (770 & 1209Hz) DTMF 5 (770 & 1336Hz) DTMF 6 (770 & 1477Hz) DTMF 7 (852 & 1209Hz) DTMF 8 (852 & 1336Hz) DTMF 9 (852 & 1477Hz) DTMF A (697 & 1633Hz) DTMF B (770 & 1633Hz) DTMF C (852 & 1633Hz) DTMF D (941 & 1633Hz) DTMF * (941 & 1209Hz) DTMF # (941 & 1477Hz) Answer tone (2100Hz) Tone (1650Hz) Answer tone (2225Hz) Tone (1300Hz)
Parameters
XMIT
Opcode: Synopsis Parameters 01
0 0 0
Start/stop Transmission
0 0 0 0 1
XMIT
XMIT start or stop the transmission of the Parallel Transmit Data. This command work only if the Parallel Transmit Data mode has been selected with a SERIAL command.
Field TX_START Byte 1 Pos. 0 Value 0* 1 Definition Stop transmission Start transmission
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VII - STATUS DESCRIPTION This appendix is dedicated to the ST75C520 reporting features. in the following sections the command acknowledge process and the report and status definitions are explained. VII.1 - Command Acknowledge and Report VII.1.1 - Command Acknowledge Process (see Figure 1) The ST75C520 features an acknowledge process based on a counter COMACK. On power-on reset (or INIT command), this counter's value is set to 0. Each time a command is successfully executed by the ST75C520, the acknowledge counter COMACK is incremented. This allows a precise monitoring of the command entered and avoids command collision. Figure 1 : Command Acknowledge Process
BEGIN
In the case of a memory reading command (CR, TDRC, TDRW, IDT or MR) once the command entered is executed, the report area is filled and the acknowledge counter is incremented afterwards. This insures that the controller will read the value corresponding to its request. Furthermore, the ST75C520 resets the value of the COMSYS register once the command has been read. The interruption IT6 is raised just after the counter is incremented. VII.1.2 - Reports Specification The report section of the Dual Port RAM is dedicated to memory reading. In response to a CR, MR, TDRC, TDRW, IDT commands, the value read is transferred to the report registers COMREP[0..1].
Yes
COMSYS = 0
No
Yes
COMMAND EXIST
No
CLEAR ANSWER
EXECUTE COMMAND
COPY ANSWER INTO COMREP
SET SY SERR ERR_IPRM
SET SYSERR ERR _IOCD
INC REMENT COMACK
ASSERT INTER RUPT IT0
ASS ERT INTE RRUP T IT0
CLEAR COMSYS
ASSERT INTERRUPT IT6
75C52006.EPS
END
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VII.1.3 - CR Command Issuing a CR command causes the ST75C520 to dump a specific memory location in complex mode. This instruction is particularly useful for equalizer state analysis or for software eye-pattern display. The report area has this meaning :
RP7 IP7 RP6 IP6 RP5 IP5 RP4 IP4 RP3 IP3 RP2 IP2 RP1 IP1 RP0 IP0 COMREP[0] COMREP[1]
RP0..RP7 is the MSB part of the 16-bit value of the real part and IP0..IP7 is the MSB part of the imaginary part. The CR command insures that the real and imaginary part of the desired complex value are sampled internally at the same time. The address given in the parameter field of CR is the address of the real part. VII.1.4 - MR/TDRC/TDRW/IDT Commands The report issued by the MR/TDRC/TDRW/IDT commands follow the same rules as for CR. The report meaning is :
D7 D15 D6 D14 D5 D13 D4 D12 D3 D11 D2 D10 D1 D9 D0 D8 COMREP[0] COMREP[1]
D0..D15 is the 16-bit value required by the MR/TDRC command. In the case of IDT, D15..D12 contains the product identification (2 for ST75C520), D11..D8 contains the hardware revision identification and D7..D0 contains the software revision identification. VII.2 - Modem Status VII.2.1 - Modem Status Description The Status of ST75C520 is divided into 4 fields : - The error status byte SYSERR that provides information about error. This status can trigger an IT0 interrupt, - The general status byte STATUS[0] and STATUS[1] that contains all the modem signals. These status bytes can trigger an IT4 interrupt, - The quality status STAQUA, that contains the quality of the received transmission, - The optional status bytes STAOP[0], STAOP[1] and STAOP[2], that contains additional information regarding the ST75C520 operatingmode. This defaultinformation can be changed to monitor any internal variables using the DOSR command. All these informations are updated on a Baud basis :
Mode Tone, DTMF, Voice Bell 103 (full duplex) V.21 (full duplex) V.23 (full duplex) V.27ter 2400bps V.27ter 4800bps V.29 V.17 V.33 V.21 channel 2 Baud Rate 2400 2400 2400 2400 1200 1600
(1) (2)
(Hz)
CLK (Hz) 9600 9600 9600 9600 2400 4800 9600/7200/4800 14400/12000/9600/7200 14400/12000 300
2400 2400 2400 2400
Notes : 1. The tone detectors outputs are update 800 times by second. 2. This baud rate defines also, the maximum command rate. Each baud time the ST75C520 looks at the COMSYS location (addesss $00) to see if a command have been sent by the host processor. If the content of this location is different from zero the ST75C520 execute the command.
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Starting at the adddress $08 the status area have the following format :
Add. $08 $09 $0A $0B $0C $0D $0E Name SYSERR Bit 7 ERR_RTK 6 5 4 3 2 STA_106 STA_CCITT 1 ERR_RX 0 ERR_TX STA_H ERR_IPRM ERR_IOCD STA_HR STA_AT Quality Depend on operating mode (see below)
STATUS0 STA_109F STA_CPT10 STA_CPT1 STA_CPT0 STA_RING STATUS1 STA_DTMF STA_FLAG STAQUA STAOP0 STAOP1 STAOP2 -
STA_107 STA_109
VII.2.2 - Error Status The error status changes each time an error occurs. When the ST75C520 signals an error by setting one of the SYSERR bit, it generates an interrupt IT0. These bits can only be cleared by the host controler using the CSE command. The meaning of the different bits of the SYSERR byte is discribed below :
Field ERR_TX ERR_RX ERR_IOCD ERR_IPRM ERR_RTK Pos. 0 1 3 4 7 SYSERR Meaning when set Transmit buffer underflow. Loss of synchronisation between the host and ST75C520 transmit data buffer managment. Receive buffer overflow. Loss of synchronisation between the host and ST75C520 receive data buffer managment. Incorrect CCI command Incorrect parameter for the CCI command Real time kernel error. ST75C520 not able to perform all its tasks within the baud period (transmit or receive samples lost).
VII.2.3 - Modem General Status The modem general status word is composed of two bytes STATUS[0] and STATUS[1]. Any bit change can generate an IT4 interrupt. Using the DSIT command allows the selection of the corresponding bit that will generate an interrupt each time they will change. The default pattern is $3F for STATUS[0] and $FF for STATUS[1]. The different bits have the following meaning :
Field STA_109 STA_107 STA_106 Pos. 0 1 2 STATUS[0] Meaning when set CCITT circuit 109 (carrier detect). Indicates that valid data are received. When 0 the output data RxD are clamped to constant mark. Valid only in modem mode. CCITT circuit 107 (data set ready). Valid only in modem mode. CCITT circuit 106 (clear to send). Indicates that the training sequence has been completed and that any data at TxD pin (serial mode) or in the transmit buffer (parallel mode) will be transmitted. valid only in modem mode. Ring detected. A ring signal (from 15Hz to 68Hz) is present at the RING pin. Valid only in tones modes. The precise frequency can be read in the optional status byte STAOP2. The detection time is 1 period of the ring signal. The detection lost time in 20ms after the last transition on the ring signal. Call progress tone detector #0. Low pass filter 650Hz. Valid only in tones modes. Call progress tone detector #1. High pass filter 600Hz. Valid only in tones modes. Signal in filter #0 is highter than #1. Valid only in tones modes. Fast Carrier Detect. Valid only in modem mode.
STA_RING
3
STA_CPT0 STA_CPT1 STA_CPT10 STA_109F
4 5 6 7
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STATUS[1] Field STA_H STA_CCITT STA_AT STA_HR STA_FLAG STA_DTMF Pos. 0 2 3 4 6 7 Meaning Transmit synchronisation in progress. Valid only in modem mode. CCITT 2100Hz versus 2225Hz answer tone detect. Valid if STA_AT is set. Valid only in tones modes. Answer tone (either 2100Hz or 2225Hz) detected. Valid only in tones modes. Receive synchronisation in progress. Valid only in modem mode. V.21 channel 2 flag detect. Valid only in FAX modem mode and tone mode. DTMF digit detect. The digit itself is available in the optional status byte STAOP2. Valid only in DTMF receive mode.
VII.2.4 - Quality Status The quality byte STAQUA monitors an evaluation of the line quality. It is updated once per baud and its value ranges from 127 (perfect quality) to 0 (terrible quality). This value is automaticaly adjusted according to the current receiving mode. Refer to the following chart to convert the value into its Bit Error Rate equivalence.
BER 1e
-2 -3 -4 -5 -6 -7
1e 1e 1e 1e 1e 1e 1e
STAQUA 0 31 63 95 127
-9
VII.2.5 - Optional Status According to the operating mode of the ST75C520 the optional status is displaying different informations. The optional status are automatically reprogrammed after each CONF command with the address of the variables to monitor according with the operating mode selected (CONF_OPER). After the CONF command the user must overwrite this default programming by using the DOSR command. VII.2.6 - Default Optional Status in Tone Mode While in tone mode the format of the STAOP word is as follows :
Add. $0C $0D $0E Name STAOP0 STAOP1 STAOP2 Bit 7 TDT7 TDT15 6 TDT6 TDT14 5 TDT5 TDT13 4 TDT4 TDT12 3 TDT3 TDT11
(1)
2 TDT2 TDT10
1 TDT1 TDT9
0 TDT0 TDT8
RING_PERIOD
Notes : 1. RING_PERIOD is valid when the bit 3 of the STATUS[0] (STA_RING) goes high. This value is updated at each falling edge of the RING signal. The RING_PERIOD value must be divided by 2400 to obtain the period in seconds. 2. TDTx is the output of the tone detector x.
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ST75C520
VII.2.7 - Default Optional Status in DTMF Receiver Mode While in DTMF receiver mode the format of the STAOP word is as follows :
Add. $0C $0D $0E Name STAOP0 STAOP1 STAOP2 Bit 7 TDT7
(1) (1)
6 TDT6
(1) (1)
5 TDT5
(1) (1)
4 TDT4 TDT12
(1) (1)
3 TDT3 TDT11
(2) (1)
2 TDT2 TDT10
(1)
1 TDT1 TDT9
(1)
0 TDT0 TDT8
(1)
TDT15
TDT14
TDT13
DTMF_DIGIT
Notes : 1. These cells are used by the DTMF detector. 2. DTMF_DIGIT is valid when the bit 7 of STATUS[1] (STA_DTMF) goes high. This value remains unchanged until a new DTMF digit is detected.
VII.2.8 - Default Optional Status in Modem Mode While in modem mode the format of the STAOP word is as follows :
Add. $0C $0D $0E Name STAOP0 STAOP1 STAOP2 PNSUCs PRDETs PNDETs Bit 7 x 6 x 5 x Not used SCR1s PRs PNs P2s P1s 4 3 SPEED (2) 2 1 0 SPVAL (1)
Notes : 1. SPVAL is active in V.33 receiver only at the same time as the rising transition of the SCR1s signal. Went SPVAL is set, it indicates that the SPEED bits contain the data speed information. 2. SPEED is valid in V.33 receiver only. It can have 2 values, after the SCR1s signal goes high : 1000 for 14400bps and 0111 for 12000bps. 3. The STAOP2 bit reflects the progression of the synchronization. The STAOP2 bits have the following meaning :
Name P1s P2s PNs PRs SCR1s PNDETs PRDETs PNSUCs
Position 0 1 2 3 4 5 6 7
Description Unmodulated carrier sequence. Optional, used for echo protection. Continuous 180 phase reversal sequence Equalizer trainning sequence V.33 and V.17 rate sequence Continuous scrambled 1 sequence Turned on after PN sequence detection Turned on after PR sequence detection (V.33 and V.17 only) Turned on after succesfull training of the receive equalizer. When on at the end of the synchronization, the transmition BER is statisticaly bellow 10ppm.
Tx X X X X X
Rx X X X X X X
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With the following timing :
P1 P2
T2
T3
PN
T4
R
T5
SCR1
T6
Data
Transmit
S TA_H
T1
P1s P2s PNs PRs
S CR1s
(6)
Receive
(7)
T7
T7
T8
T8
T8
T8
S TA_HR
S TA_109F
P2s PNDETs PNs
PRDETs
(1)
P NSUCs
(2)
S CR1s
S TA_109
75C52021.EPS
RxData
Mode V.17 V.17 short V.29 V.29 short V.27 4800 V.27 4800 short V.27 2400 V.27 2400 short
T1
(4)
T1p 30 30 30 30 30 30 30 30
(5)
T2 22 22 22 22 22 22 22 22
T3 107 107 53 41 31 9 42 12
T4 1240 16 160 26 670 36 895 48
T5 27 0 0 0 0 0 0 0
T6 20 20 20 8 5 5 7 7
T7 5 5 5 5 5 5 6 6
T8 7 7 7 7 7 7 7 7
Unit ms ms ms ms ms ms ms ms
192 192 192 192 192 192 192 192
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Data
SCR1
T10 T11 m in
Transmit
STA_H P1s P2s PN s PR s SCR1s
(6)
Receive
STA_HR STA_109F
T12
T13
(3)
PN DETs (3) PN s PR DETs (3) PN SUC s (3) STA_109
75C52022.EPS
RxData
Mode V.17 V.17 short V.29 V.29 short V.27 4800 V.27 4800 short V.27 2400 V.27 2400 short
Notes : 1. 2. 3. 4. 5. 6. 7.
T10 13 13 13 13 20 20 27 27
T11 20 20 20 20 30 30 40 40
T12 8 8 8 8 8 8 8 8
T13 25 25 25 25 25 25 25 25
Unit ms ms ms ms ms ms ms ms
In the case of V.29 or V.27, PRs and PRDETs bits are not active. PNSUC s indicates the quality of the Rx signal that will give a ber of approximation of 1e-5. After sending the command SYNC0, all bits are reset. When using long echo protection tone, otherwise 0. When using short echo protection tone, otherwise 0. STA-106 is set at the end of T6 and reset at the beginning of T10. After sending the command SYNC1, this bit is set.
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VIII - TONE DETECTORS VIII.1 - Overview The general purpose TS75C520 tone detectors block is a powerful module that covers a lot of applications : - call progress tone detection, fully programmable for all countries, - DTMF detection, - FAX, voice, data automatic detection, - call waiting detection,while in voice or data mode. VIII.2 - Description The tone detectorblock is a set of 16 identical Cells. Each cell is composed of a Double Biquadratic Filter, a Power estimator section, a Static level and a Level comparator. Figure 2 : Biquadratic IIR Filter
IN C0 C5 C6
2
Each Biquadratic Filter, Power Estimator and Static Level can be programmed using a complete set of Commands (TDRC, TDRW, TDWC, TDWW, TDZ). The wiring between the different Cells can be defined by the user, using the associatedCommand allowing a wide range of applications. The 16 Comparator Outputs give, on a baud basis, the information into two 8 bits words TONEDET0 (for cells number 0 to 7) and TONEDET1 (for cells number 8 to F). These TONEDET variables can be accessed using a MR command or, more easily, monitored on a baud basis using the DOSR command. VIII.2.1 - Biquadratic Filters Each Biquadratic Filter is a double regular section that can perform any Transfer function with 4 Poles and 4 Zeros. This routine is run on a sample basis.
CB
Z -1
OUT
2
Z -1
Z -1
C1
C3
C7
C9
Z -1
Z -1
75C52007.EPS
C2
C4
C8
CA
The corresponding transfer function is :
Out
Input
= C0
C5 + 2 C3 z
1
+ 2 C4 z
2
1 2 C1 z1 2 C2 z2
C6
CB + 2 C9 z1 + 2 CA z2 1 z 1 2 C7 z1 2 C8 z2
Note : All coefficients are coded on 16 bits 2's complement in the range +1, -1 (Q15). To avoid the possibility of overflow the user must check that the internal node must not be higher that 0.5 (in Q15 representation).
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VIII.2.2 - Power Estimation The Power estimation Cell is needed to measure the amplitude of the different tones. It is run on a sample basis. Figure 3 : Power Estimator
IN
corresponding bit into the TONEDET[0..1] word; if not it clear this bit. VIII.2.5 - Wiring The user must specify the connection (wiring) between the input/outputof the Filter, the input/output of the Power estimator, the output of the static levels and the two inputs of the Comparators. The output signals have an absolute address:
75C52008.EPS
+ ABS(.) P1
OUT Z -1
Z -1
Node Address Signal Name Ground RxSig RxSig2 RxSig4 Filter[0..F] Power[0..F] Level[0..F] Address 00 01 02 03 04..0F 10..1F 20..2F 30..3F Description Signal always equal to 0000 Receive signal from the Analog front end Receive signal multiplied by 2 Receive signal multiplied by 4 Reserved Biquadratic Filter Outputs Power Estimator Outputs Static Levels
The corresponding transfer function is :
Out =
| Input| z
1
P1 1 (1 P1) z1
VIII.2.3 - Static Level A single Threshold level is associated with each Cell. It can be use to compare the outputof a Power Estimation with an Absolute Value. VIII.2.4 - Comparator The Comparator computes, on a baud basis, the difference of the signal on its Positive and Negative Inputs. If the result is Higher that zero it sets the
The user will specify the inputs of the filters, Power and Comparator. At leastone input must come from the RxSig (node 01, 02 or 03). It is mandatory to connect all unused cell inputs to the Ground signal (node 00).
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Figure 4 : Tone Detector Wiring Address (first half)
BIQUADR ATIC FILTER #0
@10
POWER #0
LEVEL #0
@2 0 COMP. #0
@3 0
BIQUADRATIC FILTER #1
@11
POWER #1
LEVEL #1
@2 1 COMP. #1
@3 1
BIQUADRATIC FILTER #2
@12
POWER #2
LEVEL #2
@2 2 COMP. #2
@3 2 @00 GROUND
BIQUADR ATIC FILTER #3
@13
POWER #3
@2 3 COMP. #3
D0 D1 D2 D3
@3 3 @01
LEVEL #3
RX SIGNAL @02
2
BIQUADRATIC FILTER #4
@14
POWER #4
LEVEL #4
@2 4 COMP. @3 4 #4
D4 D5 D6 D7
@03
2
BIQUADRATIC FILTER #5
@15
POWER #5
LEVEL #5
@2 5 COMP. #5
TONEDET0
@3 5
BIQUADRATIC FILTER #6
@16
POWER #6
LEVEL #6
@2 6 COMP. #6
@3 6
@3 7
LEVEL #7
COMP. #7
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BIQUADRATIC FILTER #7
@17
POWER #7
@2 7
ST75C520
Figure 5 : Tone Detector Wiring Address (second half)
BIQUADRATIC FILTER #8 @18
POWER #8
LEVEL #8
@28 @38 COMP. #8
BIQUADRATIC FILTER #9
@19
POWER #9
LEVEL #9
@29 @39 COMP. #9
BIQUADRATIC FILTER #A
@1A
POWER #A
@2A @3A COMP. #A D0 COMP. #B D1 D2 D3
LEVEL #A
BIQU AD RATIC FILTE R #B
@1B
POWER #B
LEVEL #B
@2B @3B
BIQUADRATIC FILTER #C
@1C
POWER #C
@2C @3C COMP. #C
D4 D5 D6 D7
LEVEL #C
BIQUADRATIC FILTER #D
@1D
POWER #D
@2D @3D COMP. #D
TONEDET1
LEVEL #D
BIQUADRATIC FILTER #E
@1E
POWER #E
@2E @3E COMP. #E
LEVEL #E
BIQUADRATIC FILTER #F
@1F
POWER #F
@2F @3F
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COMP. #F
LEVEL #F
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VIII.3 - Example Hereunder is an example of programming a single Tone detection (using Cell #3) and a complex differential tone detection (using Cell #4 and #5). Bit 3 of the TONEDET variable will be triggered each time the energy of that filtered signal is higher than Static Level number 3. Figure 6 : Wiring Example
@00
GROUND BIQUADRATIC FILTER #3
Bit 4 of the TONEDET variable will be on each time a receive signal has an energy higher than the Static Level number 4. Bit 5 will be on only when the Filtered (Filter section 4 and 5) received signal higher than the energy of the wide-band signal number 4 ; this prevents triggering on noise.
@13
POWER #3
LEVEL #3
@23 @33
COMP. #3
RX SIGNAL
@01
BIQUADRATIC
@14
POWER #4
@24 D3 @34
COMP. #4
@02 2 @03 2
FILTER #4
D4 D5
LEVEL #4 BIQUADRATIC FILTER #5
@15
POWER #5
@25 @35
COMP. #5
TONEDET0
LEVEL #5
Program Cell #3 : TDWW 03 00 13 Connect Received signal to Filter and Filter to Energy. TDWW 03 01 33 Connect Level to Comparator Neg Input and Energy to Pos Input. Program Cell #4 and #5 : TDWW 04 00 01 Connect Received Signal to Filter and Energy. TDWW 04 01 34 Connect Level to Comparator Neg Input and Energy to Pos Input. TDWW 05 00 15 Connect Filter#4 Output to Filter and Filter to Energy. TDWW 05 01 24 Connect Wide-band Energy to Neg Input and Energy to Pos Input. IX - BUFFER OPERATIONS
01 23
01 24 14 25
IX.1 - Introduction This appendixis dedicatedto buffer operation, either the data buffersused in data exchanges or in particular Modes (like Voice). The first part is oriented towards a functional description of the buffer operation, while the second section is more oriented towards the management of the buffers.
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ST75C520
IX.2 - Receive Operations Overview Figure 7 describes the receive data flow. The ST75C520 can handle the following types of format for the data : - parallel synchronous mode : 8-bit words are synchronously available in the receive buffers. The buffer status holds the number of valid bytes received, - parallel HDLC framing mode : 8-bit data is available in the receive buffers. Framing information (like flags, CRC, additional "0") is interpreted by the ST75C520 and reported when necessary in the receive buffer status (CRC error, aborted frame, framing error, etc). This feature greatly eases the implementation of protocols as well as FAX data management. Each time the receive deframer has filled up a new buffer, it sets the correspondingflag with the proper status then generates the IT3 interrupt. The availability of the buffers is tested just before starting to Figure 7 : Rx Buffer Schematics
DA TA FO R M AT
ER ROR R X (SYSERR )
fill them. This further means that the host must not perform any buffer operation on the data part while the status remains 0. IX.3 - Transmit Operations Overview Figure 8 describes the transmit data flow. The following modes are available : - parallel synchronous mode : 8-bit words are synchronously read from the transmit buffers. The transmit status buffer holds the number of valid bytes to be transmitted (up to 8 per buffer), - parallel HDLC framing mode : 8-bit data is received from the transmit buffers. Framing information (frame open, frame close, frame abort, number of byte per buffer) is carried by the transmit buffe r s tat us a nd processed by th e ST75C520. CRC, padding and other operations are automatically handled by the ST75C520. Each time the transmit framer has emptied a buffer, the IT2 interrupt is raised.
R EC E I V E R S TA TU S
IT 3
R X B U FF E R ST A T U S
RECEIVE DEFRAMER
R EC E I V E R D ATA RX DATA BU F F E R
RX C LK
Figure 8 : Tx Buffer Schematics
D ATA FO RM A T E RR OR TX (SYSER R)
IT2
TRAN SM ITTER STATU S
SERIAL
T X B U FF E R S T A TU S
TRANSM ITTER FRAMER
TRAN SM ITTER DATA
MU X T X D AT A BUFFER
T X C LK
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S E RI AL IN
TXD
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S ER IA L OUT
RXD
ST75C520
IX.4 - Buffer Status and Format Description The following section describes the meaning and use of the buffer status words. IX.4.1 - Transmit Buffer The transmit buffer status words are DTTBS0 and DTTBS1 (see the Host Interface Summary section in the main document) and are more likely to be seen as control words. These words must be set by the host and are reset by the ST75C520. The data buffer exchanges are synchronized through these status words, (see Buffer Status and format description)an impropersetting will trigger the error Err_Tx in the error status SYSERR. A value of 0 for DTTBS0 or DTTBS1 means that the corresponding buffers are empty : this value is written by the ST75C520. The unused bits of DTTBSx must be set to 0 by the host. In FSK Mode, when working in the parallel data mode, the transmitter expands each bit to the nominal baud time (1200Hz/300Hz/75Hz). IX.4.2 - Synchronous Mode
Field BUFF_LENG Pos. 3..0 Val. 1..8 Description Number of valid bytes in the buffer BUFF_ERRS 5..4 00 01 10 11 Description Number of valid bytes in the buffer Data stream Start of frame Data stream End of frame Normal process Abort frame (no data in buffer) BUFF_SFRM BUFF_EFRM 6 7 0 1 0 1
DTRBS1 (see the Host Interface Summary section in the main document). These flags are set by the ST75C520 and must be reset by the host. The data buffer exchanges are synchronized through these status words, an improper resetting will trigger the error Err_Rx in the error status SYSERR. A value of 0 for DTRBS0 or DTRBS1 means that the corresponding buffers are empty : this value must be written by the host. In FSK or V.21 Channel 2 Mode, when working in the parallel data mode, the receiver extract each b it u s in g t h e n o min al b a u d rat e (1200Hz/300Hz/75Hz). IX.5.1 - Synchronous Mode
Field BUFF_LENG Pos. 3..0 Val. 1..8 Description Number of valid bytes in the buffer
IX.5.2 - HDLC Framing Mode
Field BUFF_LENG Pos. 3..0 Val. 1..8 Description Number of valid bytes in the buffer No error CRC error Non byte-aligned frame Aborted frame Data stream Start of frame Data stream End of frame
IX.4.3 - HDLC Framing Mode
Field BUFF_LENG BUFF_SFRM BUFF_EFRM BUFF_FRAB Pos. 3..0 4 5 6 Val. 1..8 0 1 0 1 0 1
IX.5 Receive Buffer The receive buffer status words are DTRBS0 and
IX.6 - Data Buffer Management Figure 9 shows the general flow chart for transmit data buffer management. In the transmit path, the data buffer exchanges should always begin with the filling of buffer 0, then with the update of the buffer 0 status word. The initiation of the data exchanges is initiated then with the XMIT command.
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Figure 9 : Buffer Operations Synchronization
Tx MAIN PROGRAM BEGIN INTERRUPT ROUTINE INTERRUPT NEED TO TRANSMIT 106 ON Y FILL BUFFER #0 UPDATE STATUS BUFFER #IBUFF Y FILL BUFFER #IBUFF N
N
UPDATE STATUS BUFFER #0
CLEAR IT2 IBUFF = 1 TOGGLE IBUFF XMIT ON
ENABLE IT2
RETURN
N
106 OFF or ERROR TX
Y
DISABLE IT2
XMIT OFF
CSE ERRTX (only if ERR)
Rx MAIN PROGRAM BEGIN
INTERRUPT ROUTINE INTERRUPT
N 109 ON Y WRITE $00 IN DATA STATUS BUFFER #0 AND #1
READ BUFFER #IBUFF
WRITE $00 IN DATA STATUS BUFFER #IBUFF
CLEAR IT3 IBUFF = 0 TOGGLE IBUFF ENABLE IT3 RETURN
Y 109 ON
N
75C52025.EPS / 75C52014.EPS
DISABLE IT3
CSE ERRRX (only if ERR)
41/45
ST75C520
X - DEFAULT CALL PROGRESS TONE DETECTORS Figure 10 : Call Progress Tone Detector Band 1 XI - DEFAULT ANSWER TONE DETECTORS Figure 12 : 2100Hz Answer Tone Detector
75C52015.TIF
Figure 11 : Call Progress Tone Detector Band 2
Figure 13 : 2225Hz Answer Tone Detector
75C52016.TIF
XII - ELECTRICAL SCHEMATICS Oscillator When using a third harmonic crystal oscillator in series resonance mode (RS < 40, C0 = 6pF, Pe = 0.1mW), we recommend the following schematic :
EX TA L 56 X TA L 55
2 9 .4 91 2 M Hz
3 3p F
1H
10n F
42/45
75C52023.EPS
5p F (opti onal)
75C52018.TIF
75C52017.TIF
ST75C520
XII - ELECTRICAL SCHEMATICS (continued) Figure 14
22k
220pF
40k
13.2k
TXA1
22k
2
8 3
4
1.2k
1
RXA 2 15k
1 3 8
TL072
320
20k
2 4
TL072
2.2nF
680pF
82k
20k
8
TL072 7
13.2k
TXA2
22k
5 6
4
220
4
TL072
15k
2.2nF RXA 1
6 5
40k
7
1.2k
8
22k
220pF AVDD
TIP
RING TRANSFORMER
1k
VREFP 100 nF VCM
100nF 1 0F 1 0F
1k
1k
10F
VREFN
75C52019.EPS
100nF
1k
AGND
AGND
AGND
XIII - PCB DESIGN GUIDELINES Performances of the FAX modem depends on the ST75C520 intrinsic performances and on the proper PC board layout. All aspects of the proper engineering practices, for PC board design, are beyond the scope of this paragraph. We recommend the following points : - in a 4-layer PC board : Separated digital ground and analog ground, connected together at one point, as close as possible to the ST75C520, - in a 2-layer PC board : Provide a ground grid in all space around and under components on both sides of the band and connect to avoid small islands, both AGNDR and AGNDT must be connected with very low impedance to a single point, (see Chapter I.7, Power Supply), the two 2.2nF capacitorsconnectedto the RXA1 and RXA2 Pins must be as close as possible to them, thetwo 100nFcapacitorsconnectedto the VREFPand VREFN pins must be as close as possible to them, analog and digital supplies must be connected together, at a single point, as close as possible to the chip (see Chapter I.7, Power Supply).
-
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ST75C520
TYPICAL APPLICATION
(third harmonic series resonance oscillator)
L1 1H C1 29.4912MHz Y1 5pF C2 33pF
C3 10nF
+5VA
43
49
SCCLK EOS BOS RDYS SCOUT SCIN MCI CLKOUT MC0 MC1 MC2 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SDTACK SINTR SCS SR/W SDS INT/MOT SA0 SA1 SA2 SA3 SA4 SA5 SA6 RESET DV DD DV DD DV DD
EXTAL 56
*
XTAL
55
C4 100nF
C5 10F
50 45
HALT/NOP 53 TXA1 2 TXA2 1
+5V TXA1 TXA2 DAA
+5V
+5V
51 42 44
RXA1 60 RXA2 61
R1 1.2k
RXA1
R8 470 R7 10k
54 48 47 46 26
27
AVDD 62
V REFP 58
*
D0 D1 D2 D3 D4 D5 D6 D7
DTACKl INTRl CSl
VCM 63
VREFN
57
C6 2.2F C7 2.2F
R2 1.2k
*
28 29 30 31 32 33 37 38 36 35
34
AGNDR 59
RXA2
AGNDT 64
EYEX 7 EYEY 6 EYESYNC 4 EYECLK 5
TP1 TP2
R3 1.2k
*
SR/W (WRl)
SDSl (RDl)
TXD 16 CLK
14 *
C9 100nF
R4 1.2k
C10 1F
VCM
R5 1.2k C11 1F
39
RXD 15 CD 13 RTS 11 CTS 12 RING 10
C8 100nF
A0 A1 A2 A3 A4 A5 A6
RESE Tl
17 18 19 20 21
22
R6 1.2k
AGND (connec t close to the ST75C52) TxD RxD
EBS
3
23 52
DGND 8 DGND 24 DGND
40
CLK
CDl RTSl CTSl RINGl
+5V INTEL mode +5V
9
25
V.24/RS232
41
MOTOROLA mode (select one of the two)
10F
*
C12 C13 C14 10nF 10nF 10nF
*
*
Notes : All capacitor with a "*" must be implanted close to the ST75C520 pin. All signal name ending with a "1" are active low. R3, R4, R5, R6 are needed if the hybrid will sink a current on VCM.
44/45
75C52024.EPS
ST75C520
PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK
A A2 e A1
16 17
1 64
(Seating Plane)
D2
D1
32 33
49 48
D
B C
E2 F L E1 E
K
Dimensions A A1 A2 B C D D1 D2 e E E1 E2 F K L
Min. 0.25 2.55 0.30 0.13 16.95 13.90
Millimeters Typ.
Max. 3.40 3.05 0.45 0.23 17.45 14.10
Min. 0.01 0.10 0.012 0.005 0.667 0.547
Inches Typ.
Max. 0.134 0.12 0.018 0.009 0.687 0.555
2.80
0.11
16.95 13.90
0.65
0.80
0o (min.), 7o (max.) 0.95 0.025
0.031
0.037
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
45/45
PQFP64.TBL
17.20 14.00 12.00 0.80 17.20 14.00 12.00 1.60
17.45 14.10
0.667 0.547
0.677 0.551 0.472 0.031 0.677 0.551 0.472 0.063
0.687 0.555
PMPQFP64.EPS

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